← Projects Power Electronics · Guadaloop · 2026–27

Guadaloop Wireless Power Transfer

Power Electronics Member · Guadaloop, UT Austin Hyperloop

A dynamic wireless charging track that powers a moving pod across a 100 mm air gap. It's designed for 1.2 kW at 60 V, simulated end to end in MATLAB/Simulink, with a synchronous MOSFET rectifier board for the receiver in progress and being simulated in LTspice.

MATLAB simulation on GitHub → Synchronous rectifier PCB on GitHub →

Block diagram: 100 V DC bus feeding four GaN full bridges with LCC compensation and DD track pads, coupled to a DD pod receiver, series capacitor and synchronous rectifier driving a 60 V, 20 A load — Full system: four transmitter sections on a shared 100 V bus, one receiver on the pod

1.2 kW60 V · 20 A output

~95%simulated efficiency

250 kHzswitching frequency

100 mmair gap

System design

Track: 12 × 2 ft: four 3 × 2 ft sections, each with its own DD transmitter pad
Receiver: One matching DD pad on the pod
Input / output: 100 V DC max in; 60 V, 20 A, 1.2 kW out
Compensation: LCC on each transmitter, series capacitor on the receiver (LCC-S)
Transmitters: Four GaN full bridges (16 × EPC2304) driven by LMG1210 gate drivers
Control: Shared 250 kHz timebase; adjacent sections share power by position as the pod crosses a seam; voltage PI loop
Receiver rectifier: Synchronous full bridge that switches with the receiver current instead of using diodes

Coil design

DD pad winding with two three-turn D lobes, and a 3D view of the pod receiver above a track transmitter — Each pad is two 3-turn “D” lobes wound in opposite directions; the pod pad sits 100 mm above the track

21.96 µH per pad; coupling 0.21 when aligned across the 100 mm gap.
Inductances computed with a Neumann line-integral field model, including every pad-to-pad coupling.
Pads are oriented so neighboring sections overlap with the same sign, letting power hand over smoothly at each seam.
Litz wire (about 6,000 × 42 AWG strands) to limit 250 kHz losses.

Four DD pads along the track, mutual inductance vs displacement, and required modulation along the track — Track layout, coupling vs. position, and the drive needed to hold 60 V along the track

Simulation results

Full switched-circuit Simscape runs with all five windings and 20 semiconductor models. From a cold start, every tested position on the track settles at 60.0 V and 20.0 A within about 20 ms, with an estimated 95.0–95.4% DC-to-DC efficiency.

Startup to 60 V and 20 A, steady-state ripple, coil currents, resonant capacitor voltage and gate commands — Startup, steady state, coil currents, resonant voltage and gate timing

Pod position	Output	Est. efficiency
Over a pad center	60.0 V · 20.0 A	95.0%
Over a seam between sections	60.0 V · 20.0 A	95.4%
Hardest point to drive	60.0 V · 20.0 A	95.4%
Track entrance (half off the track)	40.3 V · 13.4 A	94.2%

Output voltage and current as the pod moves along the track at 1 and 10 m/s — Moving pod (reduced model): output stays within 0.13% of 60 V at 10 m/s across all three seams

Note: These are simulation results. The coils still need to be built, measured and tuned at 250 kHz, and the receiver's resonant capacitor sees about 1.5 kV even though the output is 60 V.

In progress

Synchronous rectifier PCB

The receiver board: a full bridge of four Infineon BSC105N15LS5 MOSFETs switched in sync with the receiver's AC current, cutting the conduction loss that a diode bridge would waste at 20 A. The KiCad schematic is drawn and being checked in LTspice; board layout comes next.

Schematic of the receiver-coil terminal, series capacitors, four-MOSFET rectifier bridge and output capacitor bank — Power stage: receiver-coil input, four-MOSFET bridge and output capacitor bank

Current sensing (ADA4817 amplifier) feeds fast TLV3601 comparators that turn the sensed signals into clean logic edges.
An SN74LV4046 phase-locked loop tracks the receiver's switching frequency, with a phase-shift stage to time the gate signals.
Two LMG1210 half-bridge drivers switch the bridge, a third serves the phase-shift stage, and an LM2776 makes the −5 V rail.
Screw-terminal connection to the receiver coil, a 5 V battery input for the control electronics, and test points throughout for bring-up.

Full KiCad schematic of the synchronous rectifier — Full schematic (click to enlarge)

In progress

LTspice simulation

Before layout, the rectifier's sensing and gate-timing loop is being checked in LTspice with the vendor models for the parts on the board: ADA4817, TLV3601, 74HC4046, LMG1210 and SN74LVC1G86. The receiver is modeled as a 250 kHz source driving its series-resonant tank (24.68 µH with two 33 nF capacitors), and the circuit is built up in three steps.

Step	What it adds	Status
1. Diode-bridge baseline	Diode bridge into 100 µF and a 50 Ω test load; 0.2 Ω current shunt, ADA4817 amplifier and TLV3601 comparator	Runs: 37.9 V out, ±1.28 A coil current, clean comparator edges
2. Synchronous switching	Diodes replaced by switches (10.9 mΩ on, 580 pF output capacitance); 74HC4046 PLL locks the gate signal to the comparator; 10 ns dead time and 20 ns gate delay	Runs, but the loop hasn't settled yet; resistor values are being re-tuned from the waveforms
3. 6.78 MHz version	The same loop at 6.78 MHz with LMG1210 gate-driver models, XOR gates and a retuned tank	Set up, not yet run

LTspice waveforms: sinusoidal receiver coil current peaking near 1.28 A, and the comparator's 0 to 5 V square wave switching just after each zero crossing — Step 1: the comparator turns the coil current into a square wave whose edges trail each zero crossing by about 75–165 ns

The MOSFETs need to switch at the current's zero crossings, so that sensing delay (2–4% of the 4 µs period) has to be built into the gate timing.
The gate logic holds 10 ns of dead time between the top and bottom switch in each leg, so the two are never on at the same time.